The present invention relates generally to integrated circuits (ICs). More particularly, the invention relates to a clocking and synchronization circuitry for clocked integrated circuits.
FIG. 1 is a block diagram showing the serial transmission of data between a transmitting unit 110 and a receiving unit 120 via data lines 130 and 132. The two units share a common data clock frequency (DCL) 134 and data bits are transmitted continuously at the rate dictated by the clock pulses. Typically, frame synchronization clock (FSC) signals 136 are transmitted to synchronize the transmission of data frames. Alternatively, the FSC signals may be embedded within data frames. Examples of transmitting and receiving units include integrated circuits that operate in conjunction with one another, such as the central processing unit (CPU) of a microprocessor or digital signal processor (DSP) and input/output (I/O) devices.
Referring to FIG. 1, a conventional phase-locked loop (PLL) arrangement is used to generate a different frequency nDCL (142) on its output for internal operations in the hardware block 160, the output frequency being derived from a reference frequency. In this example, the reference frequency is provided by the common data clock (DCL). The output clock signal (nDCL) from the PLL (140) has a frequency that is a multiple (n-times) of the input DCL signal (where n is a real number from 1 to N). The clock signal nDCL serves as the internal clock signal and is propagated within the receiving integrated circuit to any ICs in the hardware block 160 generating or processing data for the transmitting device.
However, a problem exists if the clock signals DCL and nDCL are not synchronized. Power supply noise and random variations in processing, voltage and temperature conditions may cause a jitter in the PLL output clock nDCL with respect to the reference clock DCL. The effects of clock jitter range from not having any effect on the system to rendering the system completely non-functional, including loss of data integrity.
As evidenced from the above discussion, it is desirable to provide an improved synchronization circuitry for integrated circuits to maximize overall performance.
The invention relates generally to synchronization circuitry. In particular, the invention relates to improved clocking circuitry for synchronizing clock signals in integrated circuits.
According to the invention, a plurality of windows is provided to accommodate jitters in a clock signal relative to a reference clock. A plurality of delayed state cycles is generated from the clock signal for internal operations within the integrated circuit.